By Robert Pease
Newnes has labored with Robert Pease, a pace-setter within the box of analog layout to pick the superior design-specific fabric that we've got to supply. The Newnes portfolio has continuously been understand for its sensible no nonsense technique and our layout content material is in line with that culture. This fabric has been selected in response to its timeliness and timelessness. Designers will locate notion among those covers highlighting easy layout recommendations that may be tailored to state-of-the-art preferred expertise in addition to layout fabric particular to what's occurring within the box this present day. As an extra bonus the editor of this reference tells you why this can be vital fabric to have to be had always. A library needs to for any layout engineers in those fields.
*Hand-picked content material chosen by way of analog layout legend Robert Pease
*Proven top layout practices for op amps, suggestions loops, and every kind of filters
*Case histories and layout examples get you off and working in your present undertaking
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Additional resources for Analog Circuits. World Class Designs
Com 32 Chapter 1 VCC RL IL VL Vin ϩ a(s) Ri Ϫ C Va Rf Vsense Rsense (a) Vin Ri Cs ϩ 1 (Rf ϩ Ri)Cs ϩ 1 + – OP-AMP MOSFET ao Ao ts ϩ 1 s(th s ϩ 1) Vsense Ri Cs ϩ 1 (Rf ϩ Ri)Cs ϩ 1 FEEDBACK (b) Figure 1-41: MOSFET current source with lag compensation. (a) Circuit with lag components Ri , C, and Rf added. (b) Block diagram. By adding lag compensation (Figure 1-41a) the system can be stabilized to provide more phase margin. Shown in Figure 1-41b is the block diagram of the system. The lag compensation adds a zero in the loop transmission at ϪRiC and a lag pole at Ϫ(Rf ϩ Ri)C.
Hence, there must be zero DC error. w ww. T . ϭ ⎜⎜ Ϫ10 2 ⎜⎝ 10 s ϩ 10Ϫ6 s ϩ 1 ⎟⎟⎠ ⎜⎜⎝ s ⎟⎟⎠ [1-29] Plotting this loop transmission magnitude and phase yields some interesting results, as shown in Figure 1-27. 5 ms. The resultant step response of the closed-loop system is shown in Figure 1-28. Things look OK except for the oscillatory behavior on the rising edge. What’s going on here? The Bode plot of the loop transmission phase and magnitude tells the story. Although the phase margin is ﬁne, the gain margin isn’t so great, due to the underdamped pole pair.
In this example, we’ll design a closed-loop controller to regulate the output voltage (Figure 1-26). We’ll assume that the forward path compensator Gc(s) includes an integrator so that there will be zero DC error9 in Vo. As a ﬁrst attempt, let’s try a compensator transfer function of the form: Gc (s ) ϭ 4 ϫ 103 s [1-28] Phase (deg); Magnitude (dB) Reactive load example—plant 20 10 0 Ϫ10 Ϫ20 Ϫ30 Ϫ40 0 Ϫ50 Ϫ100 Ϫ150 104 105 Frequency (rad/sec) 106 Figure 1-25: Reactive load example plant Bode plot.